Hrm. There's an idea.

I'm not sure it'd actually work, but the MC14500B is simple enough with its 16 instructions that I could actually emulate an 8-bit wide, two-cycle Von Neumann version of it with, say, an Atmel MCU. Same 16 opcodes, just a wider data path and integrated program counter and return stack.

Two-cycle might not be possible, given machine word length -- which would be fixed at 4+address width bits. So, for a 16-bit address bus, that's three cycles to read in each instruction, then a cycle to execute the instruction.

It'd need 16 pins for address, 8 for data, plus /RD and /WR strobes.

So, it would be like:

Cycle 0: load opcode byte from PC address. Increment PC address.

Cycle 1: Load low address byte from PC address. Increment PC address.

Cycle 2: Load high address byte from PC address. Increment PC address.

Cycle 3: Execute instruction.

"Cycle" here meaning an emulated machine cycle, not an MCU cycle.

The code to execute the instruction could literally be a 16-case switch statement on the low four bits of the opcode byte. A 16-bit variable for PC, boolean flags for IEN and OEN, a byte variable for the result register, and functions to load and store to and from the address/data bus using GPIO pins.

Oooh, another 8 output pins for the result register, if we're really emulating the MC14500B arch.